1. Field of Invention
This invention relates to memory devices. Specifically, the present invention relates to memory controllers.
2. Description of the Related Art
Memory controllers, such as Synchronous Dynamic Random Access Memory (SDRAM), Enhanced SDRAM (ESDRAM), and Virtual Channel Memory (VCM) controllers, are employed in various demanding applications including personal computers, space and airborne computing systems, tactical infrared sensor systems, and unmanned aerial vehicle guidance systems. Such applications demand efficient memory controllers that maximize memory access speed while minimizing space requirements and design complexity and costs.
Memory controllers issue command sequences, such as read and write command sequences, to memory. Conventionally, upon issuing a command sequence to memory, the controller waits for command sequence completion before issuing a subsequent command sequence. However, as a command sequence is being serviced, often no data flows to or from the memory, resulting in undesirable data gaps that reduce memory bandwidth and efficiency.
Some memory controllers employ a pipeline state machine to reduce data gaps. Pipeline state machines may employ two interleaving state machines, which allow limited memory command, address, and data flow overlapping during data transfer, which affords improvements in memory bandwidth. Memory commands that are output from the interleaving state machines are selectively multiplexed to memory at desired times to reduce data gaps. Unfortunately, currently available memory controllers, particularly ESDRAM and SDRAM controllers, are not memory cycle time-optimized. Consequently, these controllers typically fail to maximize overlap between memory commands and data flow, which yields undesirably lengthy data gaps and compromises memory bandwidth.
Conventional memory controllers, particularly conventional ESDRAM and SDRAM controllers, are often designed for sequential data access within a memory page. In applications involving random cross-page access, memory efficiency typically varies with the complexity of the accompanying memory controller. Consequently, complex and expensive memory controllers are often required to efficiently accommodate frequent random cross-page accessing.
Hence, a need exists in the art for an efficient memory controller or cycle time optimizer that is optimized for both sequential and cross-page access applications and that minimizes requisite board space and controller complexity. There exists a further need for a memory controller that effectively minimizes data gaps caused by non-optimized memory command and data flow overlap.